1. Field of the Invention
The present invention relates to semiconductor devices having capacitive elements and manufacturing methods thereof. More particularly, the present invention relates to a semiconductor device having a plurality of metal interconnection layers on a semiconductor substrate and having a capacitive element in an opening of an insulating layer between upper and lower metal interconnection layers as well as a manufacturing method thereof.
2. Description of the Background Art
FIG. 16 is a cross sectional view schematically showing a structure of a conventional semiconductor device having a capacitive element. A capacitive element C has a lower electrode 109, a dielectric layer for capacitive element 110, and an upper electrode 112. Lower electrode 109 is formed on a surface of a semiconductor substrate 101, which is isolated by a trench isolation 102 and formed when a gate electrode 105 of a transistor T is formed. Lower electrode 109 has a stack of a polysilicon layer 109a doped with impurities and a high melting point metal film 109b of, for example, W (tungsten), Ti (titanium), Co (cobalt), Ni (nickel) or Mo (molybdenum), or a silicide 109b thereof. Upper electrode 112 is formed on lower electrode 109 with dielectric layer for capacitive element 110 interposed. Upper electrode 112 is a polysilicon or amorphous silicon doped with impurities such as P (phosphorus) or As (arsenic), or a compound of a high melting point metal film such as TiN (titanium nitride). Dielectric layer for capacitive element 110 is, for example, a high dielectric film such as a silicon oxide film, silicon nitride film or tantalum oxide film formed by CVD (Chemical Vapor Deposition).
An interlayer insulating layer 107 is formed to cover capacitive element C. Each of lower electrode 109 and upper electrode 112 is electrically connected to a metal interconnection 113 through a metal plug 108 filling in a contact hole 107a. Metal interconnection 113 applies a potential to each of lower electrode 109 and upper electrode 112, so that electric charges are accumulated between the electrodes.
Note that transistor T has a pair of source/drain regions 103, a gate insulating layer 104, and a gate electrode layer 105. The pair of source/drain regions 103 are separated on the surface of semiconductor substrate 101. Gate electrode layer 105 is formed on the region between the pair of source/drain regions 103 through gate insulating layer 104. An insulating layer 106 is formed on gate electrode layer 105. Each of the pair of source/drain regions 103 is electrically connected to metal interconnection 113 through metal plug 108 in contact hole 107a. 
In the semiconductor device having a conventional capacitive element, the surface of interlayer insulating layer 107 covering capacitive element C and transistor T is planarized by CMP (Chemical Mechanical Polishing). The planarization is performed to reduce steps at the surface of interlayer insulating layer 107, so as to facilitate pattern formation at the upper layer by photolithography for greater dimensional accuracy.
When the planarization is performed by CMP, however, the upper surface of interlayer insulating layer 107 is planarized almost completely, whereby a thickness h1 of films on gate electrode 105 becomes smaller than a thickness h3 of a film on source/drain region 103 by a thickness of gate electrode 105. Likewise, a thickness h2 of a film on upper electrode 112 becomes smaller than thickness h1 of films on gate electrode 105 by the thicknesses of dielectric layer for capacitive element 110 and upper electrode 112.
Usually, there is a variation in thickness of films removed at the time of planarization by CMP. Thus, thickness h2 must be sufficiently large to prevent exposure of upper electrode 112 from interlayer insulating layer 107 during planarization. However, as thickness h2 increases, thickness h3 of the film on source/drain region 107 inevitably increases. The increase in thickness h3 results in greater aspect ratio of contact hole 107a (a ratio of depth to diameter of contact hole 107a) reaching source/drain region 103. As a result, it becomes difficult to stably form, by dry etching, contact hole 107a with sufficient dimensional accuracy. In some cases, the etching stops en route, preventing proper formation of contact hole 107a. 
A technique for solving the aforementioned problem is disclosed in Japanese Patent Laying-Open No. 11-274428. FIG. 17 is a cross-sectional view schematically showing a structure of a semiconductor device having a capacitive element disclosed in the aforementioned laid-open application No. 11-274428. Referring to FIG. 17, capacitive element C has a lower electrode 209, a dielectric layer for capacitive element 210, and an upper electrode 212A. Lower electrode 209 is formed on a silicon oxide film 207 [209] on a silicon substrate 201, having a polysilicon film 209a and a titanium silicide film 209b. Upper electrode 212A is formed to fill in a hole 211a opened in an interlayer insulating layer 211. Upper electrode 212A is electrically connected to an aluminum interconnection 213A deposited on interlayer insulating layer 211.
Now, a method of manufacturing the semiconductor device having the capacitive element will be described.
FIGS. 18 to 23 are schematic cross sectional views sequentially showing the method of manufacturing the semiconductor device having the capacitive element shown in FIG. 17. Referring to FIG. 18, after silicon oxide film 207 is formed on silicon substrate 201, a lower electrode 209 having polysilicon film 209a and titanium silicide film 209b is formed.
Referring to FIG. 19, interlayer insulating layer 211 is formed to cover lower electrode 209. An opening 211a reaching lower electrode 209a is opened in interlayer insulating layer 211. A silicon nitride film 210, later to be a dielectric layer for capacitive element, is formed over the entire surface to cover the inner surface of opening 211a. 
Referring to FIG. 20, a contact hole 211b reaching lower electrode 209 is formed in interlayer insulating layer 211 and silicon nitride film 210.
Referring to FIG. 21, a tungsten film 212 is formed over the entire surface to fill in hole 211a and contact hole 211b. Thereafter, tungsten film 212 is polished by CMP.
Referring to FIG. 22, the upper surface of silicon nitride film 210 is exposed by CMP, so that upper electrode 211A and a plug conductive layer 212B of tungsten are formed.
Referring to FIG. 23, any unwanted portion of silicon nitride film 210, exposed from the surface, is removed by dry etching.
Thereafter, the aluminum interconnection layer is formed to complete a semiconductor device having capacitive element C as shown in FIG. 17.
In the structure shown in FIG. 17, upper electrode 212A for capacitive element C is formed as a plug layer filling in hole 211A. Thus, upper electrode 212A can be electrically connected to aluminum interconnection layer 213B directly at the upper surface of interlayer insulating layer 211. This eliminates the need for a contact hole connecting upper electrode 212A and aluminum interconnection 213B, so that the thickness of interlayer insulating layer 211 is restrained. Thus, the problem as described in conjunction with the structure of FIG. 16, associated with greater thickness h3 of the film on source/drain region 103, can be alleviated.
However, the structure shown in FIG. 17 still suffers from problems associated with a complicated manufacturing process or insufficient capacity of the capacitive element when diffusion of metal atoms from a lower electrode is considered. In the following, the problems will be described in detail.
(1) Increased number of manufacturing steps
In the structure shown in FIG. 17, for example, if copper (Cu) is used for lower electrode 209, the copper atoms easily diffuse into an insulating layer such as a silicon oxide film, causing a change of threshold voltage of the transistor or the like. Thus, lower electrode 209 is covered with a barrier layer to prevent diffusion of the copper atoms from lower electrode 209.
In the structure of FIG. 17, additional barrier layer is required for that purpose, involving additional manufacturing steps.
Alternatively, dielectric layer for capacitive element 210 can be provided with a function of preventing diffusion of copper atoms. However, in the structure of FIG. 17, dielectric layer for capacitive element 210 is formed only in hole 211a, so that the diffusion of copper atoms from lower electrode 209 cannot be reliably prevented.
(2) Capacitance of capacitive element C
In the structure of FIG. 17, lower electrode 209 and upper electrode 212A, that are opposite to each other, are flat in shape. Therefore, the capacitive element cannot ensure a sufficient capacitance.
An object of the present invention is to provide a semiconductor device having a capacitive element capable of preventing diffusion of metal atoms from a lower electrode with a streamlined manufacturing process as well as a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor device having a capacitive element allowing proper formation of a contact hole and providing increased capacitance as well as a manufacturing method thereof.
A semiconductor device having a capacitive element according to one aspect of the present invention is provided with a lower electrode layer, a dielectric layer for capacitive element, an insulating layer, and an upper electrode layer. The dielectric layer for capacitive element is formed on the lower electrode layer. The insulating layer is formed on the lower electrode layer and the dielectric layer for capacitive element and has a hole reaching the dielectric layer for capacitive element. The upper electrode layer fills in the hole and is disposed opposite to the lower electrode layer with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with an upper surface of the lower electrode layer at a region outside the region directly below the hole and the sidewall of the hole.
In the semiconductor device having the capacitive element according to one aspect of the present invention, the dielectric layer for capacitive element is in contact with the lower electrode layer not only at the region directly below the hole but also at the region outside the sidewall of the hole, so that the semiconductor device produces greater effect of preventing diffusion of metal atoms from the lower electrode layer as compared with the conventional structure (FIG. 17).
Additional diffusion barrier layer is not necessary since the dielectric layer for capacitive element also acts as such a diffusion barrier layer. Thus, additional step of forming the diffusion barrier layer is unnecessary, whereby a diffusion barrier layer with sufficient diffusion preventing effect can be provided by a streamlined manufacturing process.
The upper electrode layer is formed as a plug layer to fill in the hole opened in the insulating layer. Accordingly, the upper electrode layer is electrically connected to a portion which is later to be an interconnection, directly at the upper surface of the insulating layer. Thus, a contact hole needs not be opened to connect the upper electrode layer and interconnection portion, whereby the thickness of the insulating layer can be restrained. As a result, the problem associated with increased thickness of the insulating layer on the source/drain region of the conventional example can be alleviated.
In the semiconductor device having the capacitive element according to one aspect of the present invention, preferably, the dielectric layer for capacitive element is in contact with the side surface of the lower electrode layer.
This prevents diffusion of metal atoms from the lower electrode layer.
In the semiconductor device having the capacitive element according to one aspect of the present invention, preferably, the dielectric layer for capacitive element has a sidewall constituting a surface that is substantially continuous to the sidewall of lower electrode layer.
This enables patterning of the lower electrode layer and the dielectric layer for capacitive element with use of the same mask. Thus, as compared with the case where different masks are used for patterning the dielectric layer for capacitive element and the lower electrode layer, less masks are used.
A semiconductor device having a capacitive element according to another aspect of the present invention is provided with a first lower electrode portion, an insulating layer, a second lower electrode portion, a dielectric layer for capacitive element, and an upper electrode layer. The insulating layer is formed on the first lower electrode portion and has a hole reaching the first lower electrode portion. The second lower electrode portion has a cylindrical portion formed along the side surface of the hole and is electrically connected to the first lower electrode portion. The dielectric layer for capacitive element is formed on the second lower electrode portion. The upper electrode portion fills in the hole and is opposite to the second lower electrode portion through the dielectric layer for capacitive element.
In the semiconductor device having the capacitive element according to another aspect of the present invention, the second lower electrode portion is formed along the side surface of the hole, having a cylindrical portion. This contributes to an increase in area where the lower and upper electrode portions are opposite to each other, whereby the capacitive element may have increased capacitance.
The upper electrode layer is formed as a plug layer which fills in the hole opened in the insulating layer. Thus, the upper electrode layer can be electrically connected to a portion to be an interconnection directly at the upper surface of the insulating layer. Thus, a contact hole for connecting the upper electrode layer and the interconnection portion needs not to be provided, whereby the thickness of the insulating layer can be restrained. Consequently, the problem associated with increased thickness of the insulating layer on the source/drain region of the conventional example can be alleviated.
In the semiconductor device having the capacitive element according to another aspect, preferably, the second lower electrode portion is not positioned on the upper surface of the insulating layer.
Thus, the second lower electrode portion can be patterned as separate from the dielectric layer for capacitive element or the like.
In the semiconductor device having the capacitive element according to another aspect, preferably, the second lower electrode portion has a portion extending on the upper surface of the insulating layer.
This enables the second lower electrode portion and the dielectric layer for capacitive element and the like to be patterned by the same mask.
In the semiconductor device having the capacitive element according to another aspect, preferably, the hole is formed to have a diameter greater than the area of the first lower electrode portion when viewed from above.
The hole filled with the upper electrode layer has a greater diameter, so that the capacitance of the capacitive element can be increased.
In the semiconductor device having the capacitive element according to another aspect, preferably, a plurality of holes are formed, each reaching the first lower electrode portion. The second lower electrode portion has a portion extending along a circumferential surface of each of the plurality of holes, and the upper electrode layer is formed to fill in each of the plurality of holes.
The capacitive element can be provided with increased capacitance by convex and concave portions formed by the plurality of holes.
A method of manufacturing a semiconductor device having a capacitive element according to one aspect of the present invention is provided with steps of: forming a dielectric layer for capacitive element on a lower electrode layer; forming an insulating layer to cover the lower electrode layer and the dielectric layer for capacitive element; forming a hole in the insulating layer reaching the dielectric layer for capacitive element; and forming an upper electrode layer to fill in the hole.
In the method of manufacturing the semiconductor device having the capacitive element according to one aspect of the present invention, a hole is formed after the lower electrode layer is covered with the dielectric layer for capacitive element. Thus, the dielectric layer for capacitive element is in contact with the lower electrode not only at a region directly below the hole but also at a region outside the hole. Thus, as compared with the conventional structure (FIG. 17), the semiconductor device is provided with enhanced effect of preventing diffusion of metal atoms from the lower electrode.
The dielectric layer for capacitive element also acts as a diffusion barrier layer, so that no additional diffusion barrier layer is necessary. Thus, additional step of forming the diffusion barrier layer is unnecessary, whereby a diffusion barrier layer with enhanced diffusion preventing effect can be obtained by a streamlined manufacturing process.
The upper electrode layer is formed as a plug layer which fills in the hole opened in the insulating layer. Thus, the upper electrode layer can be electrically connected to a portion, later to be an interconnection, directly at the upper surface of the insulating layer. As a result, a contact hole for connecting the upper electrode layer and the interconnection portion needs not be formed, whereby the thickness of the insulating layer can be restrained. Consequently, the problem of the conventional example associated with increased thickness of the insulating layer on the source/drain region can be alleviated.
In the method of manufacturing the semiconductor device having a capacitive element according to one aspect, preferably, the step of forming the dielectric layer for capacitive element on the lower electrode layer has a step of forming the dielectric layer for capacitive element to cover the upper and side surfaces of the lower electrode layer after patterning the lower electrode layer.
Thus, diffusion of metal atoms from the side surface of the lower electrode layer can be prevented.
In the method of manufacturing the semiconductor device having the capacitive element according to one aspect, preferably, the step of forming the dielectric layer for capacitive element on the lower electrode layer has a step of patterning a conductive layer and the dielectric layer for capacitive element after forming the dielectric layer for capacitive element on the conductive layer later to be a lower electrode layer.
This enables patterning of the lower electrode layer and the dielectric layer for capacitive element with use of the same mask. Thus, as compared with case where the dielectric layer for capacitive element and the lower electrode layer are patterned with use of different masks, the process can be simplified.
A method of manufacturing a semiconductor device having a capacitive element according to another aspect of the present invention is provided with steps of: forming a first lower electrode portion; forming an insulating layer on the first lower electrode portion; forming a hole reaching the first lower electrode portion in the insulating layer; forming a second lower electrode portion having a portion along the side wall of the hole and electrically connected to the first lower electrode portion; forming a dielectric layer for capacitive element on the second lower electrode portion; and forming an upper electrode layer which fills in the hole and is opposite to the second lower electrode portion with the dielectric layer for capacitive element interposed.
In the method of manufacturing the semiconductor device having the capacitive element according to another aspect of the present invention, the second lower electrode portion is formed along the sidewall of the hole, hence having a cylindrical portion. This increases an area where the lower and upper electrodes are opposite to each other, so that the capacitive element may have increased capacitance.
The upper electrode layer is formed as a plug layer which fills in the hole opened in the insulating layer. Thus, the upper electrode layer can be electrically connected to a portion, later to be an interconnection, directly at the upper surface of the insulating layer. As a result, a contact hole for connecting the upper electrode layer and the interconnection portion needs not be formed, whereby the thickness of the insulating layer can be restrained. Consequently, the problem of the conventional example associated with increased thickness of the insulating layer on the source/drain region can be alleviated.
In the method of manufacturing the semiconductor device having the capacitive element according to another aspect, preferably, the step of forming the second lower electrode portion has a step of forming a conductive layer, which is later to be a second lower electrode portion, to cover the inner surface of the hole and the upper surface of the insulating layer and then patterning the conductive layer to leave it only in the hole.
This enables the second lower electrode portion to be patterned as separate from the dielectric layer for capacitive element or the like.
In the method of manufacturing the semiconductor device having the capacitive element according to another aspect, preferably, the step of forming the second lower electrode portion has a step of forming a conductive layer, which is later to be a second lower electrode portion, to cover the inner surface of the hole and the upper surface of the insulating layer and then patterning the conductive layer along with the dielectric layer for capacitive element formed on the conductive layer later to be the second lower electrode portion to leave them in the hole and at a part of the upper portion of the insulating layer.
This enables the second lower electrode portion, the dielectric layer for capacitive element and the like to be patterned by the same mask.
In the method of manufacturing the semiconductor device having the capacitive element according to another aspect, preferably, the hole is formed to have a diameter greater than the area of the upper surface of the first lower electrode portion when viewed from above.
The diameter of the hole filled with the upper electrode layer is increased, so that the capacitive element may have increased capacitance.
In the method of manufacturing the semiconductor device having the capacitive element according to another aspect, preferably, a plurality of holes are formed, each of which reaching the first lower electrode portion. The second lower electrode portion has a portion extending along the sidewall of the plurality of holes, and the upper electrode portion is formed to fill in each of the plurality of hole.
The convex and concave portions formed by the plurality of holes may provide a capacitive element with greater capacitance.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.